DSP core verification using automatic test case generation
نویسندگان
چکیده
The veriication methodology for a TMS320C25 compatible embedded DSP core is described. The DSP core has been implemented in synthesizable VHDL and has been cosimulated with the original DSP to verify correct behavior. Automatic test case generation together with hand-crafted code has been used as a means of providing stimuli to achieve increased RTL-simulation coverage. The cosim-ulation environment for this veriication and the process of automatic test case generation is described in detail. Experimental results in terms of simulation coverage are discussed. Finally, a classiication of all identiied design aws in the implementation is given and error-prone parts of the HDL design are identiied.
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